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EEPROM
Austin Semiconductor, Inc. 128K x 32 EEPROM
EEPROM Memory Array
AVAILABLE AS MILITARY SPECIFICATIONS
* *
* * * * * * *
AS8E128K32
PIN ASSIGNMENT
(Top View)
66 Lead PGA
(Pins 8, 21, 28, 39 are no connects on the PN package)
SMD 5962-94585 MIL-STD-883
Access times of 120, 140, 150, 200, 250, and 300 ns Built in decoupling caps for low noise operation Organized as 128K x32; User configurable as 256K x16 or 512K x8 Operation with single 5 volt supply Low power CMOS TTL Compatible Inputs and Outputs Operating Temperature Ranges: Military: -55oC to +125oC Industrial: -40oC to +85oC
FEATURES
66 Lead PGA
(Pins 8, 21, 28, 39 are grounds on the P package)
OPTIONS
*
MARKINGS
-120 -140 -150 -200 -250 -300 Q P PN No. 703 No. 904 No. 904 68 Lead CQFP
3 4
*
Timing 120 ns 140 ns 150 ns 200 ns 250 ns 300 ns Package Ceramic Quad Flat pack Pin Grid Array- 8 Series Pin Grid Array- 8 Series
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8E128K32 is a 4 Megabit EEPROM Module organized as 128K x 32 bit. User configurable to 256K x16 or 512Kx 8. The module achieves high speed access, low power consumption and high reliability by employing advanced CMOS memory technology. The military grade product is manufactured in compliance to the SMD and MIL-STD 883, making the AS8E128K32 ideally suited for military or space applications. The module is offered in a 1.075 inch square ceramic pin grid array substrate. This package design provides the optimum space saving solution for boards that accept through hole packaging. The module is also offered as a 68 lead 0.990 inch square ceramic quad flat pack. It has a max. height of 0.200 inch. This package design is targeted for those applications which require low profile SMT Packaging.
For more products and information please visit our web site at www.austinsemiconductor.com
AS8E128K32 Rev. 5.5 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
EEPROM
Austin Semiconductor, Inc.
DEVICE IDENTIFICATION
An extra 128 bytes of EEPROM memory is available on each die for user identification. By raising A9 to 12V + 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be written to or read from in the same manner as the regular memory array.
AS8E128K32
of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle.
TOGGLE BIT DEVICE OPERATION
The 128K x 32 EEPROM memory solution is an electrically erasable and programmable memory module that is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte-page register to allow writing of up to 128 bytes of data simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. In addition to DATA Polling the module provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 of the accessed die toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.
DATA PROTECTION
If precautions are not taken, inadvertent writes may occur during transitions of the host power supply. The E2 module has incorporated both hardware and software features that will protect the memory against inadvertent writes.
READ
The memory module is accessed like a Static RAM. When CE\ and OE\ are low and WE\ is High, the data stored at the memory location determined by the address pins is asserted on the outputs. The module can be read as a 32 bit, 16 bit or 8 bit device. The outputs are put in the high impedance state when either CE\ or OE\ is high. This dual-line control gives designers flexibility in preventing bus contention in their system.
HARDWARE PROTECTION
Hardware features protect against inadvertent writes to the module in the following ways: (a) Vcc sense - if Vcc is below 3.8 V (typical) the write function is inhibited; (b) Vcc power-on delay once Vcc has reached 3.8 V the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit - holding any one of OE\ low, CE\ high or WE\ high inhibits write cycles; (d) noise filter pulses of less than 15 ns (typical) on the WE\ or CE\ inputs will not initiate a write cycle.
BYTE WRITE
A low pulse on the WE\ or CE\ input with CE\ or WE\ low (respectively) and OE\ high initiates a write cycle. The address is latched on the falling edge of CE\ or WE\, whichever occurs last. The data is latched by the first rising edge of CE\ or WE\. Once a BWDW (byte, word or double word) write has been started it will automatically time itself to completion.
SOFTWARE DATA PROTECTION
A software controlled data protection feature has been implemented on the memory module. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user and is shipped with SDP disabled, SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the three byte command sequence and after tWC the entire module will be protected from inadvertent write operations. It should be noted, that once protected the host may still perform a byte of page write to the module. This is done by preceding the data to be written by the same three byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the 128K x 32 EEPROM during power-up and Power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the three byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
PAGE WRITE
The page write operation of the 128K x 32 EEPROM allows 1 to 128 BWDWs of data to be written into the device during a single internal programming period. Each new BWDW must be written within 150- sec (tBLC) of the previous BWDW. If the tBLC limit is exceeded the memory module will cease accepting data and commence the internal programming operation. For each WE high to low transition during the page write operation, A7-A16 must be the same. The A0-A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
DATA POLLING
This memory module features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read
AS8E128K32 Rev. 5.5 9/01
2
EEPROM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss Vcc ..............................................................................-.5V to +7.0V Storage Temperature ....................... ....................-65C to +150C Short Circuit Output Current (per I/O)................................20mA Voltage on any Pin Relative to Vss.....................-.5V to Vcc+1 V Max Junction Temperature**.............................................+150C Thermal Resistance junction to case (JC): Package Type Q...............................................11.3 C/W Package Type P & PN.......................................2.8 C/W
AS8E128K32
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity (plastics).
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC
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AS8E128K32 Rev. 5.5 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
EEPROM
Austin Semiconductor, Inc.
CAPACITANCE TABLE1 (VIN = 0V, f = 1 MHz, TA = 25oC)
SYMBOL CADD COE CWE, CCE CIO PARAMETER A0 - A16 Capacitance OE\ Capacitance WE\ and CE\ Capacitance I/O 0- I/O 31 Capacitance MAX 40 40 10 12 UNITS pF pF pF pF
AS8E128K32
NOTE: 1. This parameter is guaranteed but not tested.
TRUTH TABLE
MODE Read Write (2) Standby/Write Write Inhibit Write Inhibit Output Disable CE VIL VIL VIH X X X OE VIL VIH X (1) X VIL VIH WE VIH VIL X VIH X X High Z I/O DOUT DIN High Z
NOTES: 1. X can be VIL or VIH 2. Refer to AC Programming Waveforms
AC TEST CONDITIONS
IOL
Current Source
TEST SPECIFICATIONS
Input pulse levels...........................................V SS to 3V Input rise and fall times...........................................5ns Input timing reference levels.................................1.5V Output reference levels.........................................1.5V Output load................................................See Figure 1
Device Under Test
+
+
Vz = 1.5V (Bipolar Supply)
Ceff = 50pf
Current Source
IOH
NOTES: Vz is programmable from -2V to + 7V. IOL and IOH programmable from 0 to 16 mA. Vz is typically the midpoint of VOH and VOL. IOL and IOH are adjusted to simulate a typical resistive load circuit.
AS8E128K32 Rev. 5.5 9/01
Figure 1
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
EEPROM
Austin Semiconductor, Inc.
AS8E128K32
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 5V +10%)
DESCRIPTION
Address to Output Delay CE\ to Output Delay OE\ to Output Delay CE\ or OE\ to Output Float Output Hold from OE\, CE\ or Address, whichever comes first
SYMBOL MIN
120 MAX
120 120
140 MIN MAX
140 140 0 55 55 0
MIN
150 MAX
150 150
MIN
200 MAX
200 200
MIN
250 MAX
250 250
MIN
300 MAX UNITS
300 300 ns ns ns ns ns
tACC tCE tOE tDF tOH
0 0
50 55
0
55 55
0
55 55
0
55 55
0
55 55
0
0
0
0
AC READ WAVEFORMS(1,2,3)
tRC ADDRESS
ADDRESS VALID
tCE tCE
CE/
tDF tDF tOE tOE tOH tOH
OE\
tACC tACC
DQ
OUTPUT VALID
NOTES: 1. CE\ may be delayed to tACC-tCE after the address transition without impact on tACC. 2. OE\ may be delayed to tCE-tOE after the falling edge of CE\ without impact on tCE or by tACC-tOE after an address change without inpact on tACC. 3. tDF is specified from OE\ or CE\ whichever occurs first (CL = 5pF).
AS8E128K32 Rev. 5.5 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
EEPROM
Austin Semiconductor, Inc.
AS8E128K32
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC WRITE CHARACTERISTICS (-55oC < TA < +125oC; Vcc = 5V +10%)
Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cyce Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 50 4 50 50 10 100 150 Min Max 10 Units ms ns ns ns ns ns s ns
tOES tOES
OE\
WRITE CYCLE NO 1. (Chip Enable Controlled) t
OEH tOEH
t
WC tWC
tAS tAS
ADDRESS
AH tAH
t
ADDRESS VALID
tCS tCS
WE\
WP tWP
tCH tCH t
WPH tWPH
t
CE\
DS tDS
t
DH tDH
t
DQ
DATA VALID
tOES tOES
OE\
WRITE CYCLE NO 2. (Write Enable Controlled) tAH tAH
tOEH tOEH
ttAS AS
ADDRESS
tCS tCS
CE\
tCH tCH ttWP WP tWPH tWPH tDS tDS tDH tDH
WE\
DQ
AS8E128K32 Rev. 5.5 9/01
DATA VALID
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
EEPROM
Austin Semiconductor, Inc.
PAGE MODE CHARACTERISTICS
Symbol
tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH
AS8E128K32
Parameter
Address, OE\ Set-Up time Address, Hold time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE\ or CE\) Data Set-up Time Data, OE\ Hold Time
Min
4 50 0 0 100 50 10
Max
Unit
ns ns ns ns ns ns ns
PAGE MODE WRITE WAVEFORMS(1,2)
OE CE\
tWP tWP
WE\
tWPH tWPH
tBLC tBLC
tAS tAS
A0 - A16
tAH tAH
VA VA VA VA VA VA
VA
tDS tDS
DATA
NOTES: 1. 2. 3. 4.
VD
tDH tDH
VD VD VD VD VD
tWC tWC
VD
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 126
VD BYTE127
A7 through A16 must specify the page address during each high to low transition of WE\ (or CE\). OE\ must be high only when WE\ and CE\ are both low. VD - Valid Data VA - Valid Address
CHIP ERASE WAVEFORMS
VIH CE\ VIL VH OE\ VIH VIH t = 5 msec (min.)
S
t
S
t
H
WE\ VIL t
t
W
= tH = 10 msec (min.)
VH = 12.0V + 0.5V
AS8E128K32 Rev. 5.5 9/01
W
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
EEPROM
Austin Semiconductor, Inc.
Software Data Protection Enable Algorithm(1)
Load Data AA to Address 5555 Load Data 55 to Address 2AAA Load Data A0 to Address 5555 Load Data XX to Any Address(4) Load Last Byte to Last Address
AS8E128K32
Software Data Protection Disable Algorithm(1)
Load Data AA to Address 5555 Load Data 55 to Address 2AAA Load Data 80 to Address 5555 Load Data AA to Address 5555 Load Data 20 to Address 5555 Load Data XX to Any Address(4) Load Last Byte to Last Address Exit Data Protect State(3)
Writes Enabled
(2)
Enter Data Protect State
NOTES: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex) 2. Write Protect state will be active at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of period even if no other data is loaded. 4. 1 to 128 bytes of data are loaded.
SOFTWARE PROTECTED PROGRAM CYCLE WAVEFORM(1)(2)(3)
OE\ CE\ t WP tAS
A0-A6
t WPH
tBLC
WE\ tAH
BYTE ADDRESS
5555
A7-A16
2AAA tDS tDH 55
5555
PAGE ADDRESS
DATA
AA
A0
BYTE 0 BYTE 126 BYTE 127
t WC
1. A0-A14 of the selected I/O bytes must conform to the addressing sequence for the first three bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7-A16) of the selected I/O bytes must be the same for each high to low transition of WE\ (or CE\). 3. OE Must be high only when WE\ and CE\ are both low. AS8E128K32 Rev. 5.5 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
EEPROM
Austin Semiconductor, Inc.
DATA POLLING CHARACTERISTICS(1)
Symbol
tDH tOEH tOE tWR
AS8E128K32
Parameter
Data Hold Time OE\ Hold Time OE\ to Output Delay
(2)
Min
10 10
Max
Units
ns ns
100 0
ns ns
Write Recovery Time
NOTES: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics.
DATA POLLING WAVEFORMS
WE\
CE\ OE\ tDH I/O7
tOEH tWR t OE High-Z
A0 - A16
An
An
An
An
An
TOGGLE BIT CHARACTERISTICS(1)
Symbol
tDH tOEH tOE
Parameter
Data Hold Time OE\ Hold Time OE\ to Output Delay OE\ High Pulse Write Recovery Time
(2)
Min
10 10
Max
Units
ns ns
100 150 0
ns ns ns
t tOEPH OEHP
ItCC WR
NOTES: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics.
TOGGLE BIT WAVEFORMS(1,2,3)
WE\ CE\
tOEH tOEH
OE\
tOEHP tOE tOE
HIGH Z
tDH tDH
I/O 6
NOTES:
tWR tWR
1. Toggling either OE or CE or Both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32 Rev. 5.5 9/01
9
EEPROM
Austin Semiconductor, Inc.
AS8E128K32
MECHANICAL DEFINITIONS*
ASI Case #703 (Package Designator Q) SMD 5962-94585, Case Outline M
4 x D2 4 x D1 4xD
DETAIL A
R
Pin 1 b
0o - 7o B L1
SEE DETAIL A e A A1 D3
SMD SPECIFICATIONS SYMBOL A A1 b B D D1 D2 D3 e R L1 MIN 0.123 0.000 0.013 0.010 REF 0.800 BSC 0.870 0.980 0.936 0.050 BSC 0.005 0.035 0.045 0.890 1.000 0.956 MAX 0.200 0.020 0.017
*All measurements are in inches.
AS8E128K32 Rev. 5.5 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
EEPROM
Austin Semiconductor, Inc.
AS8E128K32
MECHANICAL DEFINITIONS*
ASI Case #904 (Package Designator P & PN) SMD 5962-94585, Case Outline 4 and 5
4xD D1 Pin 56 D2 Pin 1
(identified by 0.060 square pad)
A A1
b1
E1
e
b Pin 66 e 66 x b2
Pin 11
L
SMD SPECIFICATIONS SYMBOL A A1 b b1 b2 D D1/E1 D2 e L MIN 0.135 0.025 0.016 0.045 0.065 1.065 1.000 BSC 0.600 BSC 0.100 BSC 0.132 0.155 MAX 0.181 0.035 0.020 0.055 0.075 1.085
*All measurements are in inches.
AS8E128K32 Rev. 5.5 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
EEPROM
Austin Semiconductor, Inc. ORDERING INFORMATION
EXAMPLE: AS8E128K32Q-250/XT Device Number AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 Package Type Q Q Q Q Q Q Speed ns -120 -140 -150 -200 -250 -300 Process /* /* /* /* /* /*
AS8E128K32
EXAMPLE: AS8E128K32P-200/883C Device Number AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 AS8E128K32 Package Type P PN P PN P PN P PN P PN P PN Speed ns -120 -120 -140 -140 -150 -150 -200 -200 -250 -250 -300 -300 Process /* /* /* /* /* /* /* /* /* /* /* /*
*AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing
-40oC to +85oC -55oC to +125oC -55oC to +125oC
PACKAGE NOTES P = Pins 8, 21, 28, and 39 are grounds. PN = Pins 8, 21, 28, and 39 are no connects.
AS8E128K32 Rev. 5.5 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
EEPROM
Austin Semiconductor, Inc. ASI TO DSCC PART NUMBER CROSS REFERENCE*
ASI Package Designator Q
ASI Part #
AS8E128K32Q-120/883C AS8E128K32Q-120/883C AS8E128K32Q-140/883C AS8E128K32Q-140/883C AS8E128K32Q-150/883C AS8E128K32Q-150/883C AS8E128K32Q-200/883C AS8E128K32Q-200/883C AS8E128K32Q-250/883C AS8E128K32Q-250/883C AS8E128K32Q-300/883C AS8E128K32Q-300/883C
AS8E128K32
SMD Part #
5962-9458506HMA 5962-9458506HMC 5962-9458505HMA 5962-9458505HMC 5962-9458504HMA 5962-9458504HMC 5962-9458503HMA 5962-9458503HMC 5962-9458502HMA 5962-9458502HMC 5962-9458501HMA 5962-9458501HMC
ASI Package Designator P & PN
ASI Part #
AS8E128K32P-120/883C AS8E128K32P-120/883C AS8E128K32P-140/883C AS8E128K32P-140/883C AS8E128K32P-150/883C AS8E128K32P-150/883C AS8E128K32P-200/883C AS8E128K32P-200/883C AS8E128K32P-250/883C AS8E128K32P-250/883C AS8E128K32P-300/883C AS8E128K32P-300/883C AS8E128K32PN-120/883C AS8E128K32PN-120/883C AS8E128K32PN-140/883C AS8E128K32PN-140/883C AS8E128K32PN-150/883C AS8E128K32PN-150/883C AS8E128K32PN-200/883C AS8E128K32PN-200/883C AS8E128K32PN-250/883C AS8E128K32PN-250/883C AS8E128K32PN-300/883C AS8E128K32PN-300/883C
SMD Part #
5962-9458506H5A 5962-9458506H5C 5962-9458505H5A 5962-9458505H5C 5962-9458504H5A 5962-9458504H5C 5962-9458503H5A 5962-9458503H5C 5962-9458502H5A 5962-9458502H5C 5962-9458501H5A 5962-9458501H5C 5962-9458506H4A 5962-9458506H4C 5962-9458505H4A 5962-9458505H4C 5962-9458504H4A 5962-9458504H4C 5962-9458503H4A 5962-9458503H4C 5962-9458502H4A 5962-9458502H4C 5962-9458501H4A 5962-9458501H4C
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
AS8E128K32 Rev. 5.5 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13

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